1. Field of the Invention
This invention relates to the area of semiconductor device manufacturing and more specifically to integrated capacitor design and manufacturing and in particular for manufacturing of integrated capacitors for Dynamic Random Access Memory (DRAM) and Radio Frequency (RF) devices.
2. Description of Prior Art
In the manufacture of certain integrated circuits, it is common to use integrated thin film capacitors. In particular, the design of a Dynamic Random Access Memory (DRAM) cell typically includes one transistor and one capacitor per memory cell. In practice, when the capacitor of a particular memory cell has a stored electrical charge, a binary “1” is stored in that memory cell. Conversely, when the capacitor of a particular memory cell does not have a stored charge, a binary “0” is stored in that memory cell. To sustain functionality and dependability of memory devices, fundamental guidelines for memory system and cell design must be observed. The fundamentals of memory system and cell design are generally well established and known in the art. Many good references are available such as DRAM and SRAM, Hisashi Shichijo, ULSI devices, C. Y. Chang and S. M. Sze, Eds., chapter 7, pages 333-375, John Wiley & Sons, New York, N.Y., 2000. Additional insight may be gained from memory design references such as DRAM Circuit Design, A Tutorial, Brent Keeth and R. Jacob Baker, IEEE Press, Piscataway, N.J., 2001. Each of the foregoing references are incorporated by reference as though fully disclosed herein. It is well accepted that DRAM capacitors must retain charge in sufficient quantity to allow reliable memory read and write operation. At a minimum, this requires that charge retention time should substantially exceed practical memory refreshing intervals. In addition, storage node (memory cell) capacitance and parasitic leakage current must meet accepted fundamental guidelines. In particular, cell capacitance is generally confined to the range above twenty-five femtoFarads (fF)/cell, and preferably to the range higher than thirty fF/cell, to ensure proper immunity to soft errors and sufficient signal to noise ratio for data readout. In addition, unavoidable leakage of charge from the storage capacitor must generally be maintained on the order of 1 femtoampere (fA) per cell or less. While unavoidable, such leakage must be compensated by periodic charge replenishment, known as “refresh.” Accepted specifications for memory cells generally set the refresh interval at 64 msec. By way of example, a thirty fF capacitor is charged with one volt (V), the capacitor holds thirty femtocoulombs (fC) of charge. With approximately one fA of leakage current, such a capacitor loses ˜0.064 fC, or, equivalently approximately two millivolts (mV), of charge between successive refresh operations. Accordingly, in the foregoing example, the signal to noise ratio of the capacitor is appropriately retained at all times.
In addition, it is also accepted that cell resistance be kept to below fifty KΩ and preferably below five KΩ to maintain cell RC time constant significantly below two nsec so as to enable approximately ten nanoseconds (nsec) or lower read-write access. Further, guidelines dictate that capacitor design must minimize all sources of parasitic capacitance between the capacitor plates and the bit lines to enable high-Q storage nodes that do not pose practical limitations on overall memory speed and performance.
Early designs of DRAM integrated circuits (ICs) were implemented with planar integrated capacitors. Such simple capacitor designs used a layer of thermally grown silicon dioxide (SiO2) on a layer of doped crystalline silicon that comprised the bottom capacitor electrode, and was known as a bottom capacitor plate. The top capacitor electrodes were implemented typically with a patterned layer of doped polysilicon or metal. In general, the capacitance of such a simple capacitor of this type is given by Equation 1:                     C        =                                            ɛ              r                        ⁢            A                    d                                    (        1        )            where ∈r is the permitivity of the dielectric layer that separates the capacitor electrodes; ∈r=K∈0, where ∈0 is the permitivity of a vacuum; A is the area of the capacitor; and d is the thickness of the dielectric layer.
The evolution of DRAM technology from such simple designs has generally relied upon aggressive increases in the density of memory cells. Historically, such increases in density have led to a ×2-2.5 times reduction in memory cell area every eighteen to twenty-four months. Several approaches have been utilized in attempts to reduce the actual area on the wafer occupied by the memory cell, while maintaining cell capacitance at the required twenty-five to thirty-five fF level. These approaches have included: reducing d, increasing A, and increasing ∈r. 
Reducing the thickness (d) of the capacitor dielectric layer, while maintaining the leakage current within acceptable bounds, initially proved useful to attain planar capacitor designs up to the 1 Mb-4 Mb memory generations. Progress up to these levels was enabled by the use of improved dielectric growth techniques which made possible thinner and better insulating SiO2. Beginning with 4 Mb-16 Mb generations of memory technology, further increases in capacitance density (per actual wafer area) was achieved primarily through the advent of three dimensional (3D) capacitor designs.
Area (A) enhancement has been pursued in two primary approaches. The first approach involves constructing the capacitor over the maximized area that could be confined within the memory cell. In this approach, the passing transistor is manufactured on the wafer. The gate electrode and a passing word line are fabricated on the wafer surface with a gap between them allowing contact with the drain region of the transistor. The capacitor is produced over most of the area above the gate word line and the passing word line. The storage plate of the capacitor is interconnected to the transistor drain to complete the cell architecture. This circuit architecture is known as “stacked” capacitor design and has been implemented over the years with a variety of different approaches for the sort and shape of the area enhancement, the makeup of the contact with the drain area, the makeup of the contact with the bit line, etc.
Early stacked capacitor designs attempted to increase capacitance by stacking multiple layers of conducting and insulating films where conducting films are linked to construct multiple parallel capacitors. This approach was popular in the early days of stacked capacitor designs. Many different stacked capacitor designs and fabrication methods were invented to address the inherent difficulties of connecting interleaved conductive layers within the framework of monolithic ICs. Prominent examples of this design may be found within U.S. Pat. Nos. 4,685,197, 4,700,457, 5,021,920, 5,077,225, 5,116,776 and 6,190,964. However, none of these designs and methods were proven to be effective enough to become commercially established. While all of the designs succeeded in stacking multiple layers of alternating conductive and dielectric layers, the problems arose because the alternate conductive layers in such a capacitor must be oppositely charged. No one has yet been able to connect to the alternate layers with a high yield integrated process that results in a capacitor in which significant opposite voltages can be reliably applied to the alternate layers and in which the charge can be applied rapidly enough that the capacitor is useful in a fast memory.
Many derivations on the stacked capacitor design have been implemented with varying degrees of success, such as crown, double crown, fins, etc. Of these designs, the design known as “crown” has become popular in recent years. A crown capacitor is constructed over a hollow cylinder with a typical height of approximately one μm. The design of the crown capacitor makes use of both the internal and external area of the cylinder to gain an additional factor of area enhancement. For sub-micron memory cells using a crown design, most of the capacitance is gained at the walls of the crown rather than the bottom. Drain contacts for crown design capacitors have transitioned from hollow polysilicon plug designs into simple stud designs.
Additional area enhancement of approximately thirty to one hundred percent has been achieved by roughing the surface of the capacitor plates in a variety of etching or grainy deposition techniques. Of these, the growth of Hemispherical Grained Silicon (HSG) has become common in the industry. The use of HSG is now recognized as a means to extend conventional stacked capacitor technology with silicon electrodes (plates) and silicon based dielectrics into the range of 128 Mb-512 Mb technology nodes.
However, as stated by the 2001 International Roadmap for Semiconductor Technology (ITRS), included here by reference, conventional stacked capacitor technology has reached the limit of extendibility at the 512 Mb technology generation. Further extensions for stacked capacitor technology have been made by increases in permitivity (∈r) and some minor reduction of dielectric layer thickness (d). However, these extensions have been made possible only by replacing traditional dielectric material such as silicon oxynitride, conventionally called “NO” dielectrics, and stacked SiO2/Si3N4 or SiO2/Si3N4/SiO2, conventionally called “ONO” dielectrics, with higher K metal-oxides. According to the ITRS, further extension of stacked capacitor technology now relies on replacement of dielectric and electrode materials with each new generation of capacitor in an attempt to increase ∈r. This development path is highly undesirable and presents challenges unprecedented in the history of semiconductor technology.
The second approach for area enhancement involves producing the capacitor inside a substantially deep trench (DT) that is etched into the silicon wafer. This so called “trench” or “DT” capacitor design places the memory cell transistor and capacitor side by side on the silicon wafer. While trench design was initially viewed as fundamentally less effective than stacked design, trench etch technology has evolved to make the production of trenches with effective area enhancement in excess of ×100 commercially available.
Further improvement of trench memory cell design and isolation technology involves placing a “passing” word line above the trench, thus further improving the efficiency of wafer area utilization. Other advances in trench technology have improved cell design efficiency by implementing vertical transistors manufactured on the wall of the trench. Vertical transistor architectures serve to decouple transistor design from dimensional scaling, permitting the utilization of long channel transistors that are advantageous for improved charge retention times and cell reliability. Further area enhancement has been achieved with bottle shaped trenches and may be further extended by the usage of HSG.
However, the existing techniques for area enhancement, including stack, crown and trench designs are quickly reaching their technical limits. For example, as the surface area utilized by each capacitor decreases, size of the features of the capacitor must also, in many cases, be decreased. In the case of the crown design, as the surface area occupied by each capacitor decreases, the area (A) of the capacitor is maintained only if the features of the capacitor are grown successively higher to compensate for the loss in surface area. As this trend continues, crown capacitor designs are projected to become successively more fragile to the point that additional feature size reduction requires significant height reduction. Accordingly, eventual replacement of existing cylindrical storage nodes with a shallow trench design (known as MSCC) and finally with a pillar design (known as M-Box) is predicted before 1 Gb technology can be achieved. Despite these design changes, height limitations dictate that the height of the storage node will shrink from the currently used 1 μm to <0.6 μm. Concurrently, limitations on the conformality of deposition technology on such ever-decreasing surface areas will force phasing out the benefit of using HSG.
Clearly, this trend of area enhancement loss makes advances of stacked capacitor technology highly obstinate. Accordingly, there is a growing concern that stacked capacitor technology may hit a definite dead-end upon transition into 2 Gb technology. While the short-term prospects of trench technology are somewhat better, trench technology is also expected to follow the same path of uncertainty and need for radical changes following the transition into 1 Gb-2 Gb technology. In addition, trench technology is incompatible with any foreseen implementation of paraelectric dielectric materials such as BST and accordingly does not have even a theoretically defined path for extendibility beyond 4 Gb technology.
Accordingly, while stack, crown and trench capacitor technology may be positioned to extend conventional memory manufacturing technology into the 1 Gb technology generations, there is no clear defined path for further extension of such technology up to and beyond the 64 Gb generation.
Given that attempts at area enhancement and dielectric thickness reduction are reaching their technical limits, the industry has, as noted above, been forced to turn to achieving increases in dielectric constant (∈r). Such an aggressive trend to increase ∈r is viewed as necessary to compensate for the limitations being realized with existing area enhancement techniques. However, efforts to achieve substantial increases in ∈r have thus far been unsuccessful. In particular, increasing ∈r is generally achieved by fabricating the films that make up DRAMs from new and different materials. Introducing new film materials necessarily requires introduction of new process steps into the DRAM fabrication process and integration of these new steps into the existing DRAM process flow. DRAM process flow and process integration are composed of literally hundreds of essential processing steps. These processing steps have been developed and perfected over the years to be optimized and compatible with each other. Any introduction of new processing steps must comply with established specifications for process flow and process integration. Accordingly, the introduction of any new film materials into the DRAM design, and the deposition and etching techniques that must be integrated into the DRAM fabrication process to deposit these films, has proven to be an extremely difficult and restrictive process. The enormous cost and development time involved with this process, and the complexity of developing and optimizing the DRAM process flow for these new materials, has thus far generally proven to outweigh any gains realized from this approach.
The ITRS reveals that sustained progress in DRAM evolution will require a different dielectric material, and possibly electrode material, every year. With the evolution of DRAM memory capacitor technology requiring yearly changes to materials and designs, the future prospects for gains using such methods are, in many cases, projected to be outweighed by the technical complexity and financial cost of implementing these methods. In addition, many of the materials on which this evolution is planned to rely are currently impossible to realize for thin films. By way of example, extension beyond 4 Gb technology is predicted to depend upon the availability of ferroelectric materials and respective alloy electrodes. Such materials are unlikely to be appropriate for memory capacitor due to their Dielectric Relaxation (DR) effect. DR accounts for time dependence deterioration of charge storage that could dictate extended read-write and refresh timings, making memory access unacceptably slow. To date, ferroelectric materials, as well as some high dielectric constant materials, often referred to as “high-K” materials, have been shown to be inappropriate for DRAM applications due to severe DR effect.
While such technical and financial barriers are not necessarily insurmountable, they are likely to adversely impact cost and development time and may render the technology unacceptably complex and expensive for commercial implementation. Accordingly, there is a need for DRAM capacitor technology that is extendable to the 64 Gb node and beyond. In particular, there is a fundamental urgent need for a ×4 or more enhancement of capacitance density that can smooth the transition into high-K dielectric technology. There is a further need for a technology that will sustain maximum area enhancement as DRAM technology advances. In addition, there is a need to find a path for capacitor technology that could be realized with conventional high-K dielectric materials with K in the range from eight to thirty avoiding the uncertainty and complexity of implementing paraelectric and ferroelectric dielectrics.
It is also crucial that any technology satisfying these needs also complies with existing process flow and integration, and circumvents thermal budget issues by enabling construction of a thermodynamically stable layer stack. It is also critical that such a method allows materials to be deposited by low temperature processes so as to minimize impact on existing process flow and thermal budget and be compatible with the thermal budget and conventional DRAM process integration.
In addition, it is advantageous that any such method limit selection of electrode and dielectric materials to include elements that are already comprised in the buildup of semiconductor devices, such as Al, W and Ti, as introduction of new elements into semiconductor fabrication environment typically requires costly cross-contamination prevention and resolution. It is crucial that the foregoing be accomplished while maintaining or improving upon fundamental specifications for capacitance/cell, resistance/cell and leakage current/cell.
It is also desirable that such a process provides for self-alignment since lithography steps, and especially front-end lithography steps, are increasingly becoming a major source of increased cost and misalignment-related reduced yield that in turn further increase the cost of production per good die.
While integrated capacitors find great usage within DRAM technology, there are also other implementations of monolithic capacitors in IC technologies, such as for RF applications, analog ICs, decoupling capacitors in the interconnect layers of ICs, etc. It is therefore also advantageous that any such advances in capacitor design be applicable in these and other areas beyond DRAM technology.